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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
A Microchip Technology Company
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
Data Sheet
High-Speed-Read (40 MHz)
The High-Speed-Read instruction supporting up to 40 MHz Read is initiated by executing an 8-bit com-
mand, 0BH, followed by address bits [A 23 -A 0 ] and a dummy byte. CE# must remain active low for the
duration of the High-Speed-Read cycle. See Figure 7 for the High-Speed-Read sequence.
Following a dummy cycle, the High-Speed-Read instruction outputs the data starting from the speci-
fied address location. The data output stream is continuous through all addresses until terminated by a
low-to-high transition on CE#. The internal address pointer will automatically increment until the high-
est memory address is reached. Once the highest memory address is reached, the address pointer
will automatically increment to the beginning (wrap-around) of the address space. For example, for 2
Mbit density, once the data from address location 3FFFFH is read, the next output will be from address
location 000000H.
CE#
MODE 3
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
47 48
55 56
63 64
71 72
80
SCK
MODE 0
SI
0B
ADD.
ADD.
ADD.
X
MSB
SO
HIGH IMPEDANCE
N
D OUT
N+1
D OUT
N+2
D OUT
N+3
D OUT
N+4
D OUT
MSB
1328 F07.0
Figure 7: High-Speed-Read Sequence
?2011 Silicon Storage Technology, Inc.
14
DS25016A
06/11
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